Our dedicated High-Frequency Trading (HFT) hardware prototyping and verification lab is equipped for cutting-edge low-latency networking and signal integrity analysis. Lab Equipment & Platforms: - FPGA Hardware: AMD Xilinx Alveo (U50, U55C, U250) and Intel Agilex dev kits. - Measurement & Capture: Keysight Infiniium high-bandwidth oscilloscopes (for signal integrity and PCIe Gen5 eye-diagram testing), Exfo network packet capturing, and Endace DAG cards. - Networking Fabric: Arista 7130 ultra-low latency Layer 1 switches, customized low-latency fiber patching panels, and high-frequency clock sync infrastructure (PTP/PPS). - Testing Servers: High-density, liquid-cooled, liquid-metal overclocked server racks running custom low-jitter Linux kernels. Workspace Culture: You will work side-by-side with quantitative researchers, compiler developers, and hardware architects. Our team operates at the intersection of high-end digital board layout and low-level kernel space drivers. We value fast prototyping, comprehensive simulation (using SystemVerilog UVM), and a culture of performance where execution logic is optimized down to the nanosecond.
Key Responsibilities
Design, code, and verify low-latency FPGA acceleration pipelines using SystemVerilog or Verilog.
Implement high-speed financial protocol parsers (FIX, ITCH, OUCH) directly in FPGA fabric.
Develop custom Linux device drivers in C/C++ to interface with FPGAs over high-bandwidth PCIe Gen4/Gen5 links.
Collaborate with quantitative researchers to profile software bottlenecks and offload computing tasks to hardware.
Test and debug physical hardware configurations using logic analyzers, high-speed oscilloscopes, and simulation suites.
Required Qualifications
Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related technical discipline.
Deep experience writing synthesizable HDL (SystemVerilog/Verilog) and writing robust testbenches.
Strong proficiency in C/C++ development for bare-metal or Linux user/kernel spaces.
Familiarity with Xilinx Vivado, Intel Quartus, ModelSim, or similar EDA suites.
Understanding of TCP/IP networking, ethernet packet structures, and high-speed PCB layouts.
