Key Responsibilities
Design, code, and verify low-latency FPGA acceleration pipelines using SystemVerilog or Verilog.
Implement high-speed financial protocol parsers (FIX, ITCH, OUCH) directly in FPGA fabric.
Develop custom Linux device drivers in C/C++ to interface with FPGAs over high-bandwidth PCIe Gen4/Gen5 links.
Collaborate with quantitative researchers to profile software bottlenecks and offload computing tasks to hardware.
Test and debug physical hardware configurations using logic analyzers, high-speed oscilloscopes, and simulation suites.
Required Qualifications
Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related technical discipline.
Deep experience writing synthesizable HDL (SystemVerilog/Verilog) and writing robust testbenches.
Strong proficiency in C/C++ development for bare-metal or Linux user/kernel spaces.
Familiarity with Xilinx Vivado, Intel Quartus, ModelSim, or similar EDA suites.
Understanding of TCP/IP networking, ethernet packet structures, and high-speed PCB layouts.